Introductory VHDL from simulation to synthesis / Sudhakar Yalamanchili
| Main Author: | Yalamanchili, Sudhakar |
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| Format: | MONOGRAPHS |
| Language: | English |
| Published: |
Upper Saddle River, NJ. : Prentice Hall, 2001 |
| Subjects: |
VHDL (Computer hardware description language)
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MUT Lib 3rd Floor
| Call Number: | TK7885.7 Y34I58 |
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| Copy 1 |
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