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181106s2001 xx 000 0 eng d |
| 020 |
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|a 0130809829
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| 040 |
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|a DLC
|c MUT
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| 050 |
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4 |
|a TK7885.7
|b Y34I58
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| 100 |
1 |
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|a Yalamanchili, Sudhakar
|
| 245 |
1 |
0 |
|a Introductory VHDL from simulation to synthesis /
|c Sudhakar Yalamanchili
|
| 260 |
|
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|a Upper Saddle River, NJ. :
|b Prentice Hall,
|c 2001
|
| 300 |
|
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|a xix, 401 p. :
|b illus. ;
|c 25 cm.
|
| 650 |
|
0 |
|a VHDL (Computer hardware description language)
|
| 991 |
|
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|a MONOGRAPHS
|b 14
|c 2018-11-06 20:12:43
|d 2023-05-11 11:29:35
|e mut
|f n
|g null
|h n
|i a
|j m
|k
|l a
|m
|n a
|o
|p b
|q
|r us
|s eng
|t 2001
|v Introductory VHDL from simulation to synthesis /
|
