VLSI synthesis of DSP kernels : algorithmic and architectural transformations / Mahesh Mehendale, Sunil D. Sherlekar
| Main Author: | Mehendale, Mahesh |
|---|---|
| Other Authors: | Sherlekar, Sunil D. |
| Format: | MONOGRAPHS |
| Language: | English |
| Published: |
Boston, MA. : Kluwer Academic Pub, 2001 |
| Subjects: |
Digital integrated circuits --
> Mathematical models.
Integrated circuits -- > Very large scale integration -- > Mathematical models. Signal processing -- > Digital techniques -- > Mathematics. Transformations (Mathematics) Computer architecture. Computer algorithms. |
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| 020 | |a 0792374215 |c 5469 | ||
| 040 | |a DLC |c MUT | ||
| 050 | 4 | |a TK7874.65 |b M44V48 | |
| 100 | 1 | |a Mehendale, Mahesh | |
| 245 | 1 | 0 | |a VLSI synthesis of DSP kernels : algorithmic and architectural transformations |b / |c Mahesh Mehendale, Sunil D. Sherlekar |
| 260 | |a Boston, MA. : |b Kluwer Academic Pub, |c 2001 | ||
| 300 | |a xxiii, 209 p. : |c 25 cm. | ||
| 500 | |a Includes index. | ||
| 650 | 0 | |a Digital integrated circuits -- |x Mathematical models. | |
| 650 | 0 | |a Integrated circuits -- |x Very large scale integration -- |x Mathematical models. | |
| 650 | 0 | |a Signal processing -- |x Digital techniques -- |x Mathematics. | |
| 650 | 0 | |a Transformations (Mathematics) | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Computer algorithms. | |
| 700 | 1 | |a Sherlekar, Sunil D. | |
| 991 | |a MONOGRAPHS |b 5 |c 2018-11-06 22:31:01 |d 2022-06-02 13:48:53 |e mut |f n |g null |h n |i a |j m |k |l a |m |n a |o |p b |q |r mau |s eng |t 2001 |v VLSI synthesis of DSP kernels : algorithmic and architectural transformations / | ||